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8-Bit, High Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC08
ence and full-scale currents eliminates the need for full-scale trimming in most applications. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic input. High voltage compliance complementary current outputs are provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak output swing. In many applications, the outputs can be directly converted to voltage without the need for an external op amp. All DAC08 series models guarantee full 8-bit monotonicity, and nonlinearities as tight as 0.1% over the entire operating temperature range are available. Device performance is essentially unchanged over the 4.5 V to 18 V power supply range, with 33 mW power consumption attainable at 5 V supplies. The compact size and low power consumption make the DAC08 attractive for portable and military/aerospace applications; devices processed to MIL-STD-883, Level B are available. DAC08 applications include 8-bit, 1 s A/D converters, servo motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high-speed modems and other applications where low cost, high speed and complete input/output versatility are required.
FEATURES Fast Settling Output Current: 85 ns Full-Scale Current Prematched to 1 LSB Direct Interface to TTL, CMOS, ECL, HTL, PMOS Nonlinearity to 0.1% Maximum Over Temperature Range High Output Impedance and Compliance: -10 V to +18 V Complementary Current Outputs Wide Range Multiplying Capability: 1 MHz Bandwidth Low FS Current Drift: 10 ppm/ C Wide Power Supply Range: 4.5 V to 18 V Low Power Consumption: 33 mW @ 5 V Low Cost Available in Die Form
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog converters provide very high-speed performance coupled with low cost and outstanding applications flexibility. Advanced circuit design achieves 85 ns settling times with very low "glitch" energy and at low power consumption. Monotonic multiplying performance is attained over a wide 20 to 1 reference current range. Matching to within 1 LSB between refer-
FUNCTIONAL BLOCK DIAGRAM
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DAC08-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V =
S
15 V, IREF = 2.0 mA, -55 C TA +125 C for DAC08/08A, 0 C TA +70 C for
DAC08A/H Typ Max DAC08E Typ DAC08C Typ
DAC08C, E & H unless otherwise noted. Output characteristics refer to both IOUT and IOUT .)
Parameter Resolution Monotonicity Nonlinearity Settling Time Symbol Conditions Min 8 8 NL tS To 1/2 LSB, All Bits Switched ON or OFF, TA = 25C1 TA = 25C1 85 0.1 135 Min 8 8 85 0.19 150 Max Min 8 8 85 0.39 150 Max Units Bits Bits % FS ns
Propagation Delay Each Bit All Bits Switched Full-Scale Tempco1 Output Voltage Compliance (True Compliance) Full Range Current
tPLH tPHL TCIFS
35 35 10
60 60 50
35 35 10
DAC08E VOC Full-Scale Current Change <1/2 LSB, ROUT > 20 M typ VREF = 10.000 V R14, R15 = 5.000 k TA = +25C IFR4 - IFR2 R14, R15 = 5.000 k VREF = +15.0 V, V- = -10 V VREF = +25.0 V, V- = -12 V IREF = 2 mA VLC = 0 V 2 VLC = 0 V VIN = -10 V to +0.8 V VIN = 2.0 V to 18 V V- = -15 V VS = 15 V1 -2 0.002 -10 -10 -10 10 +18 +13.5 -3
60 60 80 50
35 35 10
60 60 80
ns ns ppm/C
-10 1.984 1.992
+18 2.000
-10 1.94 1.99
+18 2.04
-10 1.94 1.99
+18 2.04
V mA
IFR4
Full Range Symmetry Zero-Scale Current Output Current Range
IFRS IZS IOR1 IOR2
0.5 0.1 2.1
4 1 2.1
1 0.2
8 2 2.1
2 0.2
16 4
A A mA
4.2 25 0.8
4.2 25 0.8 2 -2 0.002 -10 -10 -1 8 -10 10 +18 +13.5 -3
4.2 25 0.8 2 -2 0.002 -10 -10 4 -1 8 -10 10 +18 +13.5 -3
mA nA V V A A V V A mA/s
Output Current Noise Logic Input Levels Logic "0" Logic Input "1" Logic Input Current Logic "0" Logic Input "1" Logic Input Swing Logic Threshold Range Reference Bias Current Reference Input Slew Rate Power Supply Sensitivity
VIL VIL IIL IIH VIS VTHR I15 dI/dt
PSSIFS+ PSSIFS-
-1 4 8 4 REQ = 200 RL = 100 See Fast Pulsed Ref. Info Following.1 CC = 0 pF V+ = 4.5 V to 18 V 0.0003 0.01 V- = -4.5 V to -18 V 0.002 0.01 IREF = 1.0 mA VS = 5 V, IREF = 1.0 mA VS = +5 V, -15 V, IREF = 2.0 mA VS = 15 V, IREF = 2.0 mA 5 V, IREF = 1.0 mA +5 V, -15 V, IREF = 2.0 mA 15 V, IREF = 2.0 mA 2.3 -4.3 2.4 -6.4 2.5 -6.5 33 108 135 3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
0.0003 0.01 0.002 0.01
0.0003 0.01 0.002 0.01
%IO/%V+ %IO/%V-
Power Supply Current
I+ I- I+ I- I+ I- Pd
2.3 -4.3 2.4 -6.4 2.5 -6.5 33 103 135
3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
2.3 -4.3 2.4 -6.4 2.5 -6.5 33 108 135
3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
mA mA mA mA mA mA mW mW mW
Power Dissipation
NOTES 1 Guaranteed by design. Specifications subject to change without notice.
-2-
REV. A
DAC08 TYPICAL ELECTRICAL CHARACTERISTICS
characteristics apply to both IOUT and IOUT .)
Parameter Reference Input Slew Rate Propagation Delay Settling Time Symbol dI/dt tPLH, tPHL tS Conditions TA = 25C, Any Bit To +1/2 LSB, All Bits Switched ON or OFF, TA = 25C All Grades Typical 8 35 85 Units mA/s ns ns
(@ VS =
15 V, and IREF = 2.0 mA, unless otherwise noted. Output
NOTES For DAC08NT & GT 25C characteristics, see DAC08N & G characteristics respectively. Specifications subject to change without notice
ABSOLUTE MAXIMUM RATINGS 1
PIN CONNECTIONS 16-Pin Dual-In-Line Package (Q Suffix)
Operating Temperature DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . . -55C to +125C DAC08HQ, EQ, CQ, HP, EP, CP, CS . . . . . 0C to +70C Junction Temperature (TJ) . . . . . . . . . . . . . . -65C to +150C Storage Temperature Q Package . . . . . . . . . . -65C to +150C Storage Temperature P Package . . . . . . . . . . -65C to +125C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . . 300C V+ Supply to V- Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . V- to V- plus 36 V VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Analog Current Outputs (at VS- = 15 V) . . . . . . . . . . 4.25 mA Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V- to V+ Reference Input Differential Voltage (V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Reference Input Current (I14) . . . . . . . . . . . . . . . . . . . 5.0 mA Package Type 16-Pin Hermetic DIP (Q) 16-Pin Plastic DIP (P) 20-Contact LCC (RC) 16-Pin SO (S)
JA 2 JC
16-Lead SO (S Suffix)
Units C/W C/W C/W C/W
100 82 76 111
16 39 36 35
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip, P-DIP, and LCC packages; JA is specified for device soldered to printed circuit board for SO package.
DAC08RC/883 20-Lead LCC (RC Suffix)
ORDERING GUIDE1
16-Pin Dual-In-Line Package NL 0.1% 0.19% 0.39% Hermetic DAC08AQ2 DAC08HQ DAC08Q2 DAC08EQ DAC08CQ Plastic DAC08HP DAC08RC/883 DAC08EP DAC08CP DAC08CS3 LCC Operating Temperature Range MIL COM MIL COM COM COM
NC = NO CONNECT
NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office.
REV. A
-3-
15 V, IREF = 2.0 mA, TA = 125 C for DAC08NT, DAC08GT devices; TA = 25 C for DAC08N, S DAC08G and DAC08GR devices, unless otherwise noted. Output characteristics apply to both IOUT and IOUT .)
Parameter Resolution Monotonicity Nonlinearity Output Voltage Compliance Full-Scale Current Full-Scale Symmetry Zero-Scale Current Output Current Range Symbol Conditions DAC08NT Limit 8 8 0.1 +18 -10 2.04 1.94 8 2 2.1 4.2 0.8 2 VLC = 0 V VIN = -10 V to +0.8 V VIN = 2.0 V to 18 V V- = -15 V 10 10 +18 -10 -3 0.01 DAC08N Limit 8 8 0.1 +18 -10 2.04 1.94 8 2 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 DAC08GT DAC08G DAC08GR Limit Limit Limit 8 8 0.19 +18 -10 2.04 1.94 8 4 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 8 8 0.19 +18 -10 2.04 1.94 8 4 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 8 8 0.39 +18 -10 2.04 1.94 16 4 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 Units Bits min Bits min % FS max V max V min mA max mA min A max A max mA min mA min V max V min A max A max V max V min A max % FS/% V max
DAC08 WAFER TEST LIMITS (@ V =
NL VOC IFS4 or IFS2 IFSS IZS IFS1
Full-Scale Current Change < 1/2 LSB VREF = 10.000 V R14, R15 = 5.000 k
IFS2 Logic Input "0" Logic Input "1" Logic Input Current Logic "0" Logic "1" Logic Input Swing VIL VIH IIL IIH VIS
V- = -10 V, VREF = +15 V V- = -12 V, VREF = +25 V R14, R15 = 5.000 k
Reference Bias Current I15 Power Supply PSSIFS+ Sensitivity PSSIFS- Power Supply Current Power Dissipation I+ Pd
V+ = 4.5 V to 18 V V- = -4.5 V to -18 V IREF = 1.0 mA VS = 15 V IREF 2.0 mA VS = 15 V IREF 2.0 mA
3.8 -7.8 174
3.8 -7.8 174
3.8 -7.8 174
3.8 -7.8 174
3.8 -7.8 174
mA max A max mW max
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
DICE CHARACTERISTICS
(+125C Tested Dice Available)
-4-
REV. A
DAC08
Figure 1. Pulsed Reference Operation
Figure 2. Burn-in Circuit
Figure 3. Fast Pulsed Reference Operation
Figure 4. True and Complimentary Output Operation
Figure 5. LSB Switching
Figure 6. Full-Scale Settling Time
REV. A
-5-
DAC08 -Typical Performance Characteristics
Figure 7. Full-Scale Current vs. Reference Current
Figure 8. LSB Propagation Delay vs. IFS
Figure 9. Reference Input Frequency Response
Figure 10. Reference Amp Common-Mode Range
Figure 11. Logic Input Current vs. Input Voltage
Figure 12. VTH-VLC vs. Temperature
Figure 13. Output Current vs. Output Voltage (Output Voltage Compliance)
Figure 14. Output Voltage Compliance vs. Temperature
Figure 15. Bit Transfer Characteristics
-6-
REV. A
DAC08
Figure 16. Power Supply Current vs. V+
Figure 17. Power Supply Current vs. V-
Figure 18. Power Supply Current vs. Temperature
BASIC CONNECTIONS
Figure 19. Accomodating Bipolar References
Figure 20. Basic Positive Reference Operation
Figure 21. Basic Unipolar Negative Operation
REV. A
-7-
DAC08
Figure 22. Basic Bipolar Output Operation
Figure 23. Recommended Full-Scale Adjustment Circuit
Figure 24. Basic Negative Reference Operation
Figure 25. Offset Binary Operation
-8-
REV. A
DAC08
Figure 26. Positive Low Impedance Output Operation
Figure 27. Negative Low Impedance Output Operation
Figure 28. Interfacing With Various Logic Families
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SET-UP
The DAC08 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to +4.0 mA. The full-scale output current is a linear function of the reference current and is given by: IFR =
255 x IREF, where IREF = I14. 256
Bipolar references may be accommodated by offsetting VREF or pin 15. The negative common-mode range of the reference amplifier is given by: VCM- = V- plus (IREF x 1 k) plus 2.5 V. The positive common-mode range is V+ less 1.5 V. When a dc reference is used, a reference bypass capacitor is recommended. A 5.0 V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14 should be split into two resistors with the junction bypassed to ground with a 0.1 F capacitor. For most applications the tight relationship between IREF and IFS will eliminate the need for trimming IREF. If required, full-scale trimming may be accomplished by adjusting the value of R14, or by using a potentiometer for R14. An improved method of full-scale trimming which eliminates potentiometer T.C. effects is shown in the recommended full-scale adjustment circuit. Using lower values of reference current reduces negative power supply current and increases reference amplifier negative commonmode range. The recommended range for operation with a dc reference current is +0.2 mA to +4.0 mA.
In positive reference applications, an external positive reference voltage forces current through R14 into the VREF(+) terminal (pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(-) at pin 15; reference current flows from ground through R14 into VREF(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at pin 15. The voltage at pin 14 is equal to and tracks the voltage at pin 15 due to the high gain of the internal reference amplifier. R15 (nominally equal to R14) is used to cancel bias current errors; R15 may be eliminated with only a minor increase in error.
REV. A
-9-
DAC08
REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V-. The value of this capacitor depends on the impedance presented to pin 14: for R14 values of 1.0, 2.5 and 5.0 k, minimum values of CC are 15, 37, and 75 pF. Larger values of R14 require proportionately increased values of CC for proper phase margin, such that the ratio of CC (pF) to R14 (k) = 15. For fastest response to a pulse, low values of R14 enabling small CC values should be used. If pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R14 = 1 k and CC = 15 pF, the reference amplifier slews at 4 mA/s enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) occurs in 120 ns when the equivalent impedance at pin 14 is 200 and CC = 0. This yields a reference slew rate of 16 mA/s which is relatively independent of RIN and VIN values.
LOGIC INPUTS
in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required it must be connected to ground or to a point capable of sourcing IFS; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is 36 V above V- and is independent of the positive supply. Negative compliance is given by V- plus (IREF x 1 k) plus 2.5 V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers.
POWER SUPPLIES
The DAC08 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 2 A logic input current and completely adjustable logic threshold voltage. For V- = -15 V, the logic inputs may swing between -10 V and +18 V. This enables direct interface with +15 V CMOS logic, even when the DAC08 is powered from a +5 V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V- plus ( IREF x 1 k) plus 2.5 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 1, VLC). The appropriate graph shows the relationship between VLC and VTH over the temperature range, with VTH nominally 1.4 above VLC. For TTL and DTL interface, simply ground pin 1. When interfacing ECL, an IREF = 1 mA is recommended. For interfacing other logic families, see preceding page. For general set-up of the logic control circuit, it should be noted that pin 1 will source 100 A typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when pin 1 sees a low impedance. If pin 1 is connected to a 1 k divider, for example, it should be bypassed to ground by a 0.01 F capacitor.
ANALOG OUTPUT CURRENTS
The DAC08 operates over a wide range of power supply voltages from a total supply of 9 V to 36 V. When operating at supplies of 5 V or less, IREF 1 mA is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and negative logic threshold range; consult the various figures for guidance. For example, operation at -4.5 V with IREF = 2 mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8 V total must be applied to insure turn-on of the internal bias network. Symmetrical supplies are not required, as the DAC08 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required: however, an artificial ground may be used to insure logic swings, etc. remain between acceptable limits. Power consumption may be calculated as follows: Pd = (I+) (V+) + (I-) (V-). A useful feature of the DAC08 design is that supply current is constant and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is low, typically 10 ppm/C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB. The temperature coefficient of the reference resistor R14 should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC08 decrease approximately 10% at -55C; at +125C an increase of about 15% is typical. The reference amplifier must be compensated by using a capacitor from pin 16 to V-. For fixed reference operation, a 0.01 F capacitor is recommended. For variable reference applications, see previous section entitled "Reference Amplifier Compensation for Multiplying Applications".
Both true and complemented output sink currents are provided where IO + IO = IFS. Current appears at the "true" (IO) output when a "1" (logic high) is applied to each logic input. As the binary count increases, the sink current at pin 4 increases proportionally, in the fashion of a "positive logic" D/A converter. When a "0" is applied to any input bit, that current is turned off at pin 4 and turned on at pin 2. A decreasing logic count increases IO as
-10-
REV. A
DAC08
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 4 mA to 4 mA. Monotonic operation is maintained over a typical range of IREF from 100 A to 4.0 mA.
SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically 85 ns at IREF = 2.0 mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35 ns for each of the 8 bits. Settling time to within 1/2 LSB of the LSB is therefore 35 ns, with each progressively larger bit taking successively longer. The MSB settles in 85 ns, thus determining the overall settling time of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns. The output capacitance of the DAC08 including the package is approximately 15 pF, therefore the output RC time constant dominates settling time if RL > 500 . Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values. The principal advantage of higher IREF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant.
Measurement of settling time requires the ability to accurately resolve 4 A, therefore a 1 k load is needed to provide adequate drive for most oscilloscopes. The settling time fixture shown in schematic labelled "Settling Time Measurement" uses a cascode design to permit driving a 1 k load with less than 5 pF of parasitic capacitance at the measurement node. At IREF values of less than 1.0 mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 01111111 to 10000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within 0.2% of the final value, and thus settling times may be observed at lower values of IREF. DAC08 switching transients or "glitches" are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 F capacitors at the supply pins provide full transient protection.
Figure 30. Settling Time Measurement
REV. A
-11-
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-16
0.840 (21.33) 0.745 (18.93)
1
8
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.015 (0.381) 0.008 (0.204)
Q-16
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.310 (7.87) 0.220 (5.59)
1 8
PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.100 (2.54) BSC
0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76)
15 0
0.015 (0.38) 0.008 (0.20)
SO-16
0.3937 (10.00) 0.3859 (9.80)
16 1 9 8
0.1574 (4.00) 0.1497 (5.80)
0.2550 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
E-20
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) TOP VIEW 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.200 (5.08) BSC 0.100 (2.54) BSC
3 4 1
0.358 (9.09) 0.342 (8.69) SQ
0.100 (2.54) 0.064 (1.63)
19 18 20
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
BOTTOM VIEW
14 13 8 9
45 TYP 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC
-12-
REV. A
PRINTED IN U.S.A.
000000000
16
9
0.280 (7.11) 0.240 (6.10)

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